1. Field
Various embodiments described herein relate to an access control device, an information processing device, an access control program and an access control method.
2. Description of the Related Art
Conventionally, a nonvolatile memory such as a flash memory, which is provided in an information processing device, includes a plurality of banks in which a plurality of memory blocks formed in units of predetermined memory cells have been arrayed. For example, as illustrated in FIG. 9, in a nonvolatile memory 700, N+1 banks (Bank0 to BankN) having the plurality of memory blocks are provided horizontally in a row.
More specifically, in each bank, two dies, that is, Die0 and Die1 are provided horizontally in a row. In each die, M+2 memory blocks, that is, Block0 to BlockM+1, and two SRAMs (Static Random Access Memories), that is, SRAM0 and SRAM1 are provided. Block0 to BlockM+1 are arranged vertically in two columns (a column of Block0, Block2, . . . BlockM, and a column of Block1, Block3, . . . BlockM+1) on each die. Moreover, SRAM0 temporarily stores data to be written to the memory blocks belonging to the column of Block0, Block2, . . . BlockM (a column of even numbers), and SRAM1 temporarily stores data to be written to the memory blocks belonging to the column of Block1, Block3, . . . BlockM+1 (a column of odd numbers). In addition, each memory block has L+1 memory cells referred to as “pages” (page0 to pageL) which have been divided in units of a plurality of bits.
When data is written to the nonvolatile memory 700 as described above, the information processing device sets a combination of particular memory blocks existing in the respective banks, as one group, and writes the data to a plurality of the memory blocks in each group at a time. Specifically, the information processing device sets a combination of memory blocks, each of which is located at the same position in an order from a beginning of each memory block column, as one group.
For example, as illustrated in FIG. 9, the information processing device sets a combination of memory blocks, each of which is located at the beginning of each memory block column, (Block0 and Block1 in each die) as one group, and writes the data to the plurality of memory blocks belonging to the above described group, at a time. In this way, the information processing device attempts to improve processing speed by writing the data to each bank in parallel. It should be noted that the groups included in the nonvolatile memory 700 are a group #1 to a group #K, respectively, in the order from the beginning of each memory block column.
Incidentally, a defective block may exist in the nonvolatile memory. The defective block is a memory block including a memory cell in which the data cannot be recorded. Some defective blocks have already existed since shipment from a factory. In addition, some good blocks have degraded due to repeated use and have become the defective blocks.
In a conventional nonvolatile memory, even if only one defective block exists in the same group, the data is not written to all the memory blocks in the group including the above described defective block, in order to maintain write performance. For example, as illustrated in FIG. 9, it is assumed that hatched memory blocks 710a to 710d, that is, Block2 in Die0 of Bank0 (the memory block 710a), Block2 in Die1 of Bank0 (the memory block 710b), Block3 in Die1 of Bank0 (the memory block 710c), and BlockM in Die0 of BankN (the memory block 710d) are the defective blocks. In this case, the information processing device does not write the data to the group including the memory blocks 710a to 710c and the group including the memory block 710d. 
It should be noted that the information processing device manages whether or not the data can be written to each group, in a memory management table. As illustrated in FIG. 10, the memory management table stores, for each of the group #1 to the group #K included in the nonvolatile memory 700, write enable/disable information indicating whether or not the data can be written to the above described group (that is, whether or not the above described group includes the defective block). For example, since the group #K includes the defective block 710d (see FIG. 9), as the write enable/disable information corresponding to the group #K, “disable” indicating that the data cannot be written to the above described group is stored in the memory management table. When the information processing device writes the data, the information processing device decides the group to which the data is written, with reference to this memory management table.
As described above, if the data is not written to all the memory blocks in the group including the defective block, the good block belonging to the above described group also cannot be used, which thus causes a problem of a reduced storage capacity which can be practically used. In other words, in such a case as illustrated in FIG. 9, the data cannot be written to BlockM, Block3 and BlockM+1 in Die0 of Bank0, BlockM and BlockM+1 in Die1 of Bank0, Block2, Block3 and BlockM+1 in Die0 of BankN, as well as Block2, Block3, BlockM and BlockM+1 in Die1 of BankN, which are the good blocks.
In order to solve the above problem, for example, an access control method for effectively using the good blocks in the nonvolatile memory has been disclosed in Japanese Patent Laid-Open No. 2004-265162. Specifically, as illustrated in FIG. 11, each one of memory blocks belonging to each of a plurality of banks (Bank0 to Bank3) is selected while the defective block is avoided, and the selected memory blocks are grouped. In other words, if the defective block is included in the memory blocks belonging to the same address of the respective banks (that is, in a conventional group), another memory block belonging to the same bank as that of the above described defective block (that is, the memory block belonging to another group) is used instead of the above described defective block.
For example, as illustrated in FIG. 11, in a group consisting of the memory blocks located in Address0 of the respective banks, it is assumed that the memory block located in Address0 of Bank1 is the defective block. Instead of the defective block located in Address0 of Bank1, the memory block located in Address5 of Bank1 is used to write the data. In other words, the memory block in Address0 of Bank0, the memory block in Address5 of Bank1, the memory block in Address0 of Bank2, and the memory block in Address0 of Bank3 (memory blocks attached with a number “1” in FIG. 11) are set as one group. In this way, while the data is simultaneously written to all the banks similarly to conventional techniques, the good block to which the writing cannot be performed in the conventional nonvolatile memory can be used.
However, in the access control method disclosed in Japanese Patent Laid-Open No. 2004-265162, when the data is written, the data is simultaneously written to all the banks. Therefore, for example, if the defective blocks are concentrated in one bank, the good block may not be able to be effectively used. For example, as illustrated in FIG. 11, each bank has eight memory blocks denoted as Address0 to Address7, respectively. Among them, it is assumed that one defective block exists in each of Bank0, Bank2 and Bank3, while five defective blocks exist in Bank1.
In such a case, when the data is written, seven good blocks to which the writing can be performed exist in each of Bank0, Bank2 and Bank3, while only three good blocks are left in Bank1. Therefore, only three groups can be generated. Thus, four of the seven good blocks existing in each of Bank0, Bank2 and Bank3 (the memory blocks in Address4 to Address7 of Bank0, the memory blocks in Address3 and Address5 to Address7 of Bank2, and the memory blocks in Address4 to Address7 of Bank3) become the good blocks to which the data cannot be written.